The present invention relates to a semiconductor integrated circuit and an operating method thereof and particularly to a technology effective in implementing an automatic selection used to select again a power supply to be used out of a plurality of power supplies in response to an electric power failure.
As has been described in, for example, each of the following Patent Documents 1 and 2, an IC card is equipped with a semiconductor integrated circuit and an antennal coil, and the supply of power to the IC card is performed by receiving an RF signal outputted from a reading/writing device called a card reader/car writer by the antenna coil and rectifying the same by a rectifier circuit. Thus, the IC card having no power supply on its card side is becoming pervasive in an automatic ticket system, e-cash, logistics management, etc. Thus, since the IC card is RF-power supplied and on the other hand, unique identification information (ID information) has been stored in a built-in non-volatile memory, it is called an RFID card.
On the other hand, a wireless power delivery system has been in widespread use which is called “just-to-place charging” in which a portable device such as a smart phone is simply placed in a dedicated charging table without coupling the portable device to a power supply cable to thereby enable the charging of the portable device. This type of wireless power delivery system intends to cope with the fact that the battery drain of the cellular phone called “smart phone” is large. That is, the smart phone is a multifunction cellular phone having a high affinity to Internet and based on the functions of a personal computer, or a multifunction cellular phone with a PDA function added to a phone/mail, which may be abbreviated as “smapho” or “smaho”. The wireless power delivery system is based on the international standard called Qi (chi) established by Wireless Power Consortium (WPC) of the industry group. Both of a transmission side device and a reception side device are respectively provided with coils to thereby enable the supply of power from the transmission side device to the reception side device by an electromagnetic induction system. The advantages of the wireless power delivery system are that there is no need to plug or unplug a power connector for charging and the operation of opening and closing a connector cover for a power connector of a portable device in particular can be omitted.
Further, it has been described in the following Patent Document 3 that in an electronic device selectively coupled to two or more types of power supplies to charge a battery, a controller is used to couple the electronic device to another power supply soon when the coupling to the power supply subjected to the supply of power is released, to thereby start the charging of the battery. That is, the control provided by the controller resides in that the battery is charged by an AC power supply while current is being supplied from the AC power supply to an AC coupling part, whereas while current is being supplied from an external device to an external device coupling part without the supply of current from the AC power supply to the AC coupling part, the battery is charged by the power supply of the external device. When the external device coupling part is coupled to the external device while the battery is being charged by the AC power supply, the controller particularly performs an initial communication with the external device to thereby conduct charge settings necessary to charge the battery through the external device. Specifically, the external device coupling part is a USB coupling part, and an interface of another standard such as IEEE1394 or the like can also be adopted. Since the current from the AC power supply is larger than that from the external device when the electronic device is coupled to both of the AC power supply and the external device, the controller serves to charge the battery through the AC power supply.
There has been described in the following Patent Document 4, a power switch IC in which a source-to-drain path of a first N channel power MOS transistor is coupled between first input and output terminals, a source-to-drain path of a second N channel power MOS transistor is coupled between second input and output terminals, and a source-to-drain path of a third N channel power MOS transistor is coupled between third input and output terminals. A drain-to-source path of a third MOS transistor is coupled between the gate of the third N channel power MOS transistor and a ground potential. A drain-to-source path of a fourth MOS transistor is coupled between the gate of the second N channel power MOS transistor and the ground potential. A drain-to-source path of a fifth MOS transistor is coupled between the gate of the first N channel power MOS transistor and the ground potential. A first input terminal is coupled an input terminal of a first inverter circuit and an input terminal of a second inverter circuit. A second input terminal and a third input terminal are coupled to a power supply terminal of the first inverter circuit and a power supply terminal of a second inverter circuit respectively. An output terminal of the first inverter circuit is coupled to the gate of the third MOS transistor. An output terminal of the second inverter circuit is coupled to the gate of the fourth MOS transistor. The output terminal of the first inverter circuit and the output terminal of the second inverter circuit are coupled to two input terminals of a two-input NOR gate circuit. Further, an output terminal of the two-input NOR gate circuit is coupled to an input terminal of a third inverter circuit. An output terminal of the third inverter circuit is coupled to the gate of the fifth MOS transistor. When the potential of the first input terminal is reduced due to the occurrence of a malfunction, the output terminal of the first inverter circuit, the output terminal of the second inverter circuit and the output terminal of the third inverter circuit become high in level, so that the third MOS transistor, the fourth MOS transistor and the fifth MOS transistor are respectively brought to an on state. Accordingly, all the power MOS transistors of the first N channel power MOS transistor coupled between the first input and output terminals, the second N channel power MOS transistor coupled between the second input and output terminals, and the third N channel power MOS transistor coupled between the third input and output terminals are controlled to an off state respectively.